Title: Design of a 128-bit AES Block Cipher Processor on FPGA
Year of Publication: 2017
Publisher: International Journal of Computer Systems (IJCS)
ISSN: 2394-1065
Series: Volume 04, Number 12, December 2017
Authors: Jung Hwan Oh, Sang Muk Lee, Seung Eun Lee


Jung Hwan Oh, Sang Muk Lee, Seung Eun Lee, "Design of a 128-bit AES Block Cipher Processor on FPGA", In International Journal of Computer Systems (IJCS), pp: 172-175, Volume 4, Issue 12, December 2017. BibTeX

	author = {Jung Hwan Oh, Sang Muk Lee, Seung Eun Lee},
	title = {Design of a 128-bit AES Block Cipher Processor on FPGA},
	journal = {International Journal of Computer Systems (IJCS)},
	year = {2017},
	volume = {4},
	number = {12},
	pages = {172-175},
	month = {December}


Advanced Encryption Standard (AES), most widely used to encrypt or decrypt data, is computationally intensive application. In order to implement the AES encryption algorithm, the data must go through complicated operations composed of several steps. In this paper, we propose a 128-bit AES block cipher processor, which supports hardware based multi-processor scheduler for high performance computing system. The functionality of the AES processor was verified on FPGA along with a hardware scheduler.


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Security, Block Cipher, FPGA, System-on-Chip, Multi-Processor, Hardware Scheduler