Papers

Title: Design and Implementation of Memory Controller for Real Time Image Acquisition using DDR2 SDRAM
Year of Publication: 2017
Publisher: International Journal of Computer Systems (IJCS)
ISSN: 2394-1065
Series: Volume 04, Number 6, June 2017
Authors: Shweta A Mandaki, Dr H P Rajani

Citation:

Shweta A Mandaki, Dr H P Rajani, "Design and Implementation of Memory Controller for Real Time Image Acquisition using DDR2 SDRAM ", In International Journal of Computer Systems (IJCS), pp: 138-144, Volume 4, Issue 6, June 2017. BibTeX

@article{key:article,
	author = {Shweta A Mandaki, Dr H P Rajani},
	title = {Design and Implementation of Memory Controller for Real Time Image Acquisition using DDR2 SDRAM},
	journal = {International Journal of Computer Systems (IJCS)},
	year = {2017},
	volume = {4},
	number = {6},
	pages = {138-144},
	month = {June}
	}


Abstract

The phenomenal development in the field of microelectronics has motivated the design engineer to integrate the complex systems of several million transistors in a single chip. There has been dynamic progression in the design of electronic systems, gadgets etc with evolving complexity and higher transaction speed. The evolution of fast and sophisticated state-of-art electronic system like processors and embedded systems, is fueled by the rapid development in the design and implementation of memory controllers. The design of DDR2 SDRAM controller can be done and implemented using FPGA technology to minimize the time to market and cost. The enhancement/improvement in the design of memory controller has led to achieve good support for memory and I/O devices. This project work deals with capturing of real time images using camera and then storage and retrieval in efficient manner. The image is stored in JPEG format, transmitted over UART communication protocol to the FPGA and then it is written (stored) on chip memory of FPGA. Image data written in organized manner in FPGA will be further read and then transmitted to the VGA screen for the display of the real time image. The results are verified by real time display of the stored data and by using simulation and synthesis tools. This project deals with the designing of efficient memory controller for DDR2 SDRAM device. This project provides thorough explanation for the design and implementation of DDR2 SDRAM controller using Xilinx Design Suit 14.6 on FPGA board.

References

[1] Arun S. Tigadi, Veenabai A. L., and Hansraj Guhilot, “Design and implementation of memory controller for real time video display using ddr3 sdram,” International Research Journal of Engineering and Technology (IRJET), Volume: 03 Issue: 07, July-2016.
[2] Arun S. Tigadi, Padmashree G., and Hansraj Guhilot, “Design and implementation of memory controller for real time video acquisition using ddr3 sdram,” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 5, Issue 8, August 2016.
[3] Difference between SDRAM, DDR SDRAM, DDR2 SDRAM https://www.transcend-info.com/Support/FAQ-296.
[4] Webcam https://en.wikipedia.org/wiki/Webcam.
[5] http://www.circuitbasics.com/basics-uart-communication Basics of UART Communication – Circuit Basics.
[6] TMS320DM357 DDR2 Memory Controller User's Texas Instruments,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprug38&fileType=pdf.


Keywords

DDR2 SDRAM, FPGA-Spartan 3A, Xilinx design suite 14.6, UART Communication Protocol, Webcam.